Monday, December 27, 2004

Hey, Nano, what are your measurements?

Glimpse Into Tomorrow: Nanotech Metrology (By Alexander E. Braun, Senior Editor -- Semiconductor International)

    The future of nanotech metrology is being shaped in advanced laboratories such as NIST's (Gaithersburg, Md.) Nanoelectronic Device Metrology Project, headed by Curt Richter. The project team is developing metrology to enable new nanotechnologies (such as silicon-based quantum devices, molecular electronics and organic thin-film transistors) to supplement or supplant conventional CMOS devices. Richter makes the point that by "metrology" NIST means measurement as opposed to industry, which views it as online process monitoring. Thus, much of NIST's "metrology" industry would call "analytical characterization," which is what is needed today to meet future device needs.

    NIST aims at developing metrology that will enable emerging information processing technologies to extend electrical performance beyond incremental CMOS scaling. Their approach considers two categories. One is molecular electronics — a bottom-up paradigm for fabrication with some self-assembly playing a role in it — which is different from typical CMOS-directed fabrication. Richter believes that some bottom-up processing will become important, and this will be a process fabrication area requiring metrology.

    The other area is silicon-based nanoelectronics, a CMOS extrapolation, down to quantum dots and quantum wires fabricated from silicon. Here, the focus is on fundamental building blocks — the quantum dot and wire themselves — and how to extract physical dimensions and make test structures for the actual probing of nanocomponents' electrical properties, not just stray structure artifacts. Electrical metrology in test structures is a primary characterization need for these research devices and materials.

    NIST pursues a broad-based approach by anticipating what will have to be measured and what a test platform to probe nanocharacteristics (not artifacts) would look like. Silicon-based nanoelectronics originates from a top-down approach, extending traditional fabrication approaches to the nano level. This requires one set of tools — how to measure an oxide or dielectric thickness on a 3-D object instead of a planar one, or correlating the test of an easily tested 2-D planar area so it directly relates to a 3-D area. For a bottom-up approach, different characterization tools are needed. More here

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